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1/4 INCH VGA CIS CAMERA MODULE
PRELIMINARY
SX5437M21X-X0B0
SX5437M21X-X0B0 (1/4 " VGA C IS Camera Module)
PRELIMINARY Preliminary Specification
Revision 1.3 May. 2004
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SX5437M21X-X0B0
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1/4 VGA CIS CAMERA MODULE
DOCUMENT TITLE
1/4" Optical Size 640x480(VGA) CIS Camera Module
REVISION HISTORY
Revision No. 0.0 0.1 0.2 1.0 History Initial draft Added register map and changed timing diagram Added module dimension Fixed some bugs Changed I2C timing diagram Changed product code (S5X437CX03-20R0 SX5437M21X-X0B0) Changed the register map Stroke out the register map (published a new document, `Register Map for 437') Modified the optical characteristics Draft Date Aug 14, 2003 Oct. 31, 2003 Remark Preliminary Preliminary
Nov. 19, 2003 Preliminary Dec. 31, 2003 Preliminary
1.1 1.2 1.3
Jan. 7, 2004 Apr.29, 2004
Preliminary Preliminary Preliminary
PRELIMINARY
May.4, 2004
This document is a general product description and is subject to change without any notice.
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1/4 INCH VGA CIS CAMERA MODULE
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SX5437M21X-X0B0
INTRODUCTION
The SX5437M21X-X0B0 is fully functional camera module with a built-in lens. A low-noise low-power color CMOS image sensor, S5K437CX03 and an image signal processor, S5C7323X produce high-quality digital video output including CCIR656 format with maximum 30 frames per second for full frame readout. With SAMSUNG 0.35m CMOS image sensor process technology which is dedicated to higher sensitivity and lower-dark level compared to standard CMOS process, and on-chip CDS and 10-bit column ADC circuit embedded, the CMOS image sensor provides high signal-to-noise ratio with low power consumption. This compact camera system consists of an image sensor, a signal processor and some passive components packed with IR-cut filter and lens units. The system works with 2.8V single power supply and a clock. All the functions are controlled with control register setting through the standard 2-wire serial interface.
FEATURES
-- Optical Size: 1/4 inch format -- Unit Pixel: 5.6 m X 5.6 m -- Effective Resolution: 640(H) X 480(V), VGA -- 8.5mm X 9.5mm X 6.6mm module size -- 8-bit ITU.R-656 (YCrCb) Video Output -- Programmable Gamma Correction -- Auto White Balance and Auto Exposure Control -- Horizontal and/or Vertical Mirror Output -- Standby-Mode for Power Saving -- Maximum 30 Frame per Second -- I2C Type Control Interface -- Bad Pixel Replacement Function -- Noise Canceling Function -- Shading Correction Function
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-- Single Power Supply Voltage: 2.8V
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SX5437M21X-X0B0
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1/4 VGA CIS CAMERA MODULE
BLOCK DIAGRAM
GNDC VDDCA VDDCD
GNDI VDDI
S5K437CA03 CMOS Image Sensor Lens Unit 10-bit ADC
S5C7323X Image Signal Processor
Line Buffer
Pixel Array 640(H) X 480(V)
Pre Processor Luminance Signal Processor Chroma Signal Processor
Timing Controller Post Processor MCLK Output Formatter VSYNC HSYNC PCLK DATA[0:7]
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RISC Processor (AE, AWB processor) I2C Bus
SDA SCL STBY RST
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SX5437M21X-X0B0
OPTICAL CHARACTERISTICS
Characteristic Effective Pixels Pixel Size EFL F/# Diagonal FOV Horizontal Vertical TV-Distortion Relative Illumination Center MTF 0.7 Field Lens Construction Focus Range Value 640 (H) X 480 (V), VGA 5.6m (H) X 5.6m (V), square pixel 3.385mm 2.8 67.87 56.44 43.59 -0.33% 54.40% 59.90% at 80 lp/mm 72.60% at 50 lp/mm 21.30% at 80 lp/mm 42.30% at 50 lp/mm All Plastic Lens (2P) 22cm ~
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1/4 VGA CIS CAMERA MODULE
MODULE PAD DESCRIPTION
(Module pad numbers and name can be changed as customer's request.) Module Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Connector Pin No. (*) 9 10 15 16 11 12 20 17 18 19 8 7 6 5 4 3 2 1 13 9 14
Name VDDDI GNDI SCL SDA RST STBY MCLK VSYNC HSYNC PCLK DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 GNDC VDDDC VDDAC
Type Power Ground In/Out In/Out In In In Out Out Out Out Out Out Out Out Out Out Out Ground Power Power
Description Power supply for signal processor (digital) Ground for signal processor I2C serial communication clock I2C serial communication data Reset control (active low) Standby control(active low) Master input clock Vertical synchronization clock Horizontal synchronization clock Pixel output clock
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8-bit digital video output Ground for sensor circuit block Power supply for sensor digital circuit block Power supply for sensor analog circuit block
NOTES: (*) See [Cf] p. 32.
PAD 1
PAD 21
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SX5437M21X-X0B0
MAXIMUM ABSOLUTE RATINGS
Characteristic Maximum supply voltage (VDDDI, VDDAC, VDDC supply relative to GNDI, GNDC) DC Input voltage *Operating temperature *Storage temperature Symbol VDD VIN TOPR TSTG Rating -0.3 to 3.8 -0.3 to VDD+0.3 (Max. 3.8) *-20 to +60 *-40 to +85 C Unit V
NOTES: *Operating temperature and *Storage temperature are not confirmed.
ELECTRICAL CHARACTERISTICS
DC Characteristics (TA = -20 to +60C, CL = 15pF) Characteristics Operating voltage Input voltage (1) Input leakage current(1) High level output voltage Low level output voltage High-Z output leakage current (4) Supply current Symbol VDD VIH VIL IIL Condition VDDCA, VDDCD, VDDI Min 2.55 2.05 Typ 2.8 Max 3.1 0.8 10 V TBD 0.2VDD 10 TBD A A mA Unit V V A
PRELIMINARY
VIN = VDD to VSS IOH = -1mA(2) IOH = -4mA(3) IOL = 1mA(2) IOL = 4mA(3) VOUT = VDD STBY = Low (active) All input clocks = Low fMCLK = 12MHz, 15fps -10 VOH 0.8VDD VOL IOZ ISTB IDD
NOTES: 1. MCLK, RSTN, STBY, SCL, and SDA pin. 2. HSYNC, VSYNC, SCL, and SDA pin 3. PCLK, YCO0 to YCO7 pin 4. SCL and SDA pin when in High-Z output state
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1/4 VGA CIS CAMERA MODULE
Sensor Imaging Characteristics
(Light source with 3200K of color temperature and IR cut filter (CM-500S, 1mm thickness) is used. Electrical operating conditions follow the recommended typical values. The control registers are set to the default values. The ambient temperature, TA is 25C if not specified.) Characteristic Saturation level(1) Sensitivity (G)(2) Dark level(3) Dynamic range(4) Signal to noise ratio(5) Dark signal non-uniformity(6) Photo response nonuniformity(7) Vertical fixed pattern noise(8) Horizontal fixed pattern noise(9) Symbol VSAT S VDARK DR S/N DSNU PRNU VFPN HFPN TA = 60C TA = 40C TA = 60C Condition Min 850 Typ 900 1500 9 50 60 40 4 4 4 Max 18 100 100 8 8 8 Unit mV mV/lux sec mV/sec
dB mV/sec % % %
NOTES: 1. Measured minimum output level at 100lux illumination for exposure time 1/30 sec. 7X7 rank filter is applied for the whole pixel area to eliminate the values from defective pixels. 2. Measured average output at 25% of saturation level illumination for exposure time 1/30 sec. Green channel output values are used for color version. 3. Measured average output at zero illumination without any offset compensation for exposure time 1/30 sec. 4. 20 log (saturation level/ dark level RMS noise excluding fixed pattern noise). 10-bit ADC limits 60dB. 5. 20 log (average output level/RMS noise excluding fixed pattern noise) at 25% of saturation level illumination for exposure time 1/30 sec. 6. Difference between maximum and minimum pixel output levels at zero illumination for exposure time 1/30 sec. 7X7 median filter is applied for the whole pixel area to eliminate the values from defective pixels. 7, Difference between maximum and minimum pixel output levels divided by average output level at 25% of saturation level illumination for exposure time 1/30 sec. 7X7 median filter is applied for the whole pixel area to eliminate the values from defective pixels. 8. For the column-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for neighboring 7 columns at 25% of saturation level illumination for exposure time 1/30 sec. 9. For the row-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for neighboring 7 columns at 25% of saturation level illumination for exposure time 1/30 sec.
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SX5437M21X-X0B0
AC Characteristics (VDDH = 2.8V 0.25V, VDDL = 1.8V 0.15V, Ta = -20 to + 60 C, CL = 50pF) Characteristic Main input clock frequency Output data delay time from PCLK Reset input pulse width Standby input pulse width Symbol fMCLK tDLY tWRST tWSTB Condition Duty = 50% Ta =0~70 RSTN=low(active) STBYN=low(active) Min 3(1) 0.7 5 4 Typ 24.54 Max 30 3.5 Unit MHz ns TMCLK(2)
NOTES: 1. 8-bit ADC resolution case. If 10-bit ADC resoultion is used, the frequency should be over 12MHz. 2. The period time of main input clock, MCLK.
(VDDH = 2.8V 0.25, Ta = 0 to + 70 C) Characteristic Output Data Delay Time, Data [0:7]
PCLK VCK
Symbol TDLY
Min 0.7
Typ -
Max 3.5
Unit ns
Data [0:7] YC9~0
PRELIMINARY
Tdly
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Setup and Hold Time
(VDDL = 1.8V 0.15, Ta = 0 to + 70 C) Characteristic Output Data Setup Time, Data [0:7] Output Data Hold Time, Data [0:7] Symbol TSU THD Min 0.217 0.217 Typ Max Unit ns ns
DATA [0:7]
50%
50%
CLK Tsu
50% Thd
Rise and Fall Transition Time
(VDDL = 1.8V 0.15, Ta = 0 to + 70 C) Characteristic Output Data, Data [0:7] Symbol TR TF Min Typ Max 4.709 4.338 Unit ns ns
PRELIMINARY
90% 90% 10% TF
10% TR
OUTPUT IMAGE MODE
No. 1 Mode VGA Resolution (H X V) 640 X 480 Data rate (PCLK) MCLK Zoom Frame Rate 30 FPS
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OUTPUT DATA FORMAT
YCRCB 4:2:2 FORMAT
VSYNC
HSYNC DATA (Mode1) DATA (Mode2) DATA (Mode3) DATA (Mode4)
Y0
CB0
Y1
CR0
Y0
CB0
Y1
CR0
Y0
CR0
Y1
CB0
Y0
CR0
Y1
CB0
CB0
Y0
CR0
Y1
CB0
Y0
CR0
Y1
CR0
Y0
CB0
Y1
CR0
Y0
CB0
Y1
RGB565 FORMAT
VSYNC HSYNC DATA (Mode1)
PRELIMINARY
RG0 GB0 RG1 GB1 RG0 GB0
R0[4:0] / G0[5:3] G0[2:0] / B0[4:0]
RG1
GB1
DATA (Mode2)
BG0
GR0
BG1
GR1
BG0
GR0
BG1
GR1
B0[4:0] / G0[5:3]
G0[2:0] / R0[4:0]
SENSOR RAW IMAGE (BAYER MOSAIC PATTERN) FORMAT
VSYNC HSYNC DATA
D0H
D0L
D1H
D1L
D0H
D0L
D1H
D1L
6'b000000, D0[9:8]
D0[7:0]
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1/4 VGA CIS CAMERA MODULE
OUTPUT TIMING DIAGRAMS
HORIZONTAL TIMING
Address : FAh[7:6]=0, F6h[7:0]=30 1 row HSY NC Address : FAh[5:4]=2, F7h[7:0]=B0
PCLK ( 640 columns ) DATA [0:7]
VGA OUTPUT TIMING
Address : FAh[3:2]=0, F8h[7:0]=03 Address : FAh[1:0]=0, F9h[7:0]=05 1 frame V SYNC 1 row HSY NC
2H
DATA [0:7]
PRELIMINARY
(480 rows ) (525 rows )
NOTES: 1. Falling and rising time of HSYNC and VSYNC can be controlled by register settings. 2. Each default value of rising and falling time control registers is described in the diagram above.
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SX5437M21X-X0B0
IMAGE PROCESSING FUNCTIONS
Function Defect detection and correction De-mosaic Description If enabled, the function detects the defective pixel by comparing its level with horizontally neighboring pixels, and replaces it with the average value of neighboring pixels. The sensor produces one color component from a pixel according to Bayer color filter array. The de-mosaic function performs color interpolation to produce all three-color components at each pixel location. The spectral response of image sensor is different from that of human eye. To match the spectral response, the sensor output components are pivoted by user programmable 3X3 matrix production. Gamma correction translating the linear response of the sensor into the non-linear characteristics of the display. Nonlinear conversion requires a piecewise linear approximation method based on user programmable lookup table. The output image can be mirrored in horizontal direction. The output image can be mirrored in vertical direction. Enhancing the edge component provides a clear output image. The edge enhancement function is performed through horizontal and vertical edge detecting and enhancing. Remarks
Color correction
Gamma correction
Horizontal mirror Vertical mirror Edge enhancement
Auto exposure
PRELIMINARY
4 types of output format are available.
According to the incident light level, the auto exposure function controls the sensor gain and effective integration time to maintain the proper output level. Setting the control registers can change the sensing area used in the AE algorithm. The auto white balance function adjusts the gain of the sensor's red and blue channels relative to the green channel, and compensates the spectral unbalancing of the light source. Setting the control registers can change the sensing area used in the AWB algorithm. (CCIR656 format, CCIR601 format, RGB format and sensor raw image output format)
Auto white balance
Output format conversion
Sub-sampling Control
The user can read out the pixel data in sub-sampling rate in both horizontal and vertical direction. Sub-sampling can be done in two rates: full and 1/2. The user controls the subsampling using the Sub-sampling Control Registers, subsr and subsc. The sub-sampling is performed only in the Bayer space.
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1/4 VGA CIS CAMERA MODULE
I2C SERIAL INTERFACE
The I2C contains a serial two-wire half duplex interface that features bi-directional operation, master or slave mode. The general SDA and SCL are the bi-directional data and clock pins, respectively. These pins are opendrain type ports and will require a pull-up resistor to VDD. The image sensor operates in salve mode only and the SCL is input only. The I2C bus interface is composed of following parts: START signal, 7-bit slave device address (0101101Xb) transmission followed by a read/write bit, an acknowledgement signal from the slave, 8-bit data transfer followed by an acknowledgement signal and STOP signal. The SDA bus line may only be changed while SCL is low. The data on the SDA bus line is valid on the high-to-low transition of SCL.
SDA SCL
"0" START "1" "0" "1" "1" "0" "1" "0"
A7
A6
A5
A4
A3
A2
A1
A0
W RITE ACK
ACK
SDA SCL
PRELIMINARY
D7 D6 D5 D4 D3 D2 D1 D0
BUS ADDRESS
REGISTER ADDRESS
ACK
STOP
DAT A
I2C Bus Write Format
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1/4 INCH VGA CIS CAMERA MODULE
PRELIMINARY
SX5437M21X-X0B0
SDA SCL
"0" START "1" "0" "1" "1" "0" "1" "0"
A7
A6
A5
A4
A3
A2
A1
A0
BUS ADDRESS
W RITE ACK
REGISTER ADDRESS
ACK
D7
D6
D5
D4
D3
D2
D1
D0
SDA
SCL
RESTART
"0"
"1"
"0"
"1"
"1"
"0"
"1"
"1" READ ACK NO ACK STOP
BUS ADDRESS
DAT A
PRELIMINARY
I2C Bus Read Format
SDA
tHIGH
SCL
tHD:S TA tLOW tHD:BYTE tHD:S TA
tHD:S TO
tHD:BUF
I2C Bus Timing
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PARAMETER SCL clock frequency Low period of the SCL clock High period of the SCL clock Hold time START condition Hold time STOP condition Bus free time between BYTE and BYTE data Bus free time between a STOP and START condition
NOTES:
Symbol fClk tLOW tHIGH tSTA tSTO tBYTE tBUF
Min 1.3 0.6 0.6 0.6 130 130
Max 400
Unit kHZ sec sec sec sec tMCLK tMCLK
1. tMclk : Main clock period
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SX5437M21X-X0B0
MODULE DIMENSION
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(c)2003 Samsung Electronics All right reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics. Samsung Electronics Co., Ltd. San #24 Nongseo-Ri, Giheung-Eup Yongin-City, Gyeonggi-Do, Korea C.P.O. Box #37, Suwon 449-900 Homepage: http://www.samsungsemi.com/
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